A 14nm FinFET Sub-Picosecond Jitter Fractional-N Ring PLL for 5G Wireless Communication

This paper presents a ring-VCO based sub-picosecond RMS jitter fractional-N PLL by employing a 31x reference multiplier to provide 60dB suppression on the ΔΣ quantization noise. By using 4-bit automatic bias calibration (ABC) and two-step digitally calibrated replica-biased regulator (DCRR), the effect of supply noise on MDLL and VCO is vastly alleviated to ensure robust jitter performance even in noisy SoC environment. Implemented in a 14nm FinFET process, the proposed PLL achieves <; 1ps
_RMS
jitter at 7GHz while consuming 36.3mW. This PLL guarantees that the ADC achieves an SNDR greater than 52dB at 400MHz bandwidth, thereby greatly relieving the data conversion requirements in 5G wireless communication.