A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM

We present a low jitter, DTC-based analog fractional-N PLL with novel, background DTC gain calibration and reference clock duty cycle correction for high performance applications. The PLL achieves a 75-fs rms jitter, integrated from 10 kHz to 10 MHz and a −249.7 dB figure of merit at fractional mode. The measured fractional-N spurs are less than −64 dBc across the 5.5-7.3 GHz output frequency. Implemented in 28-nm CMOS, this PLL consumes 18.9 mW and occupies 0.5 mm
²
.