Design of the trigger system for the Auger fluorescence detector

A description of the trigger system for the 13 200 channels of the Auger fluorescence detector is presented. The concept for the front-end electronics, the first and second level trigger, the data flow and the data processing rests upon the system requirements. The design uses FPGAs to obtain a cost-effective and flexible solution whenever possible. The large scale integration of the modern FPGA allowed a massive parallel solution for recognition of tracks and suppression of background. The supervision task and readout is carried out by low cost PCs under LINUX operating system.