Pattern recognition algorithms on FPGAs and CPUs for the ATLAS LVL2 trigger

Recent studies of the level-two (LVL2) trigger of the ATLAS detector show that the trigger algorithms for high luminosity runs can potentially be executed in general-purpose processors, using a sequential selection scheme and a LVL1 Region-of-Interest (RoI) guidance. However, the most stringent requirements in terms of computing power come from potential B-physics events investigated at low luminosity. For these events, there is no LVL1 guidance available for the track search, therefore a global pattern recognition in the whole Inner Detector volume has to be done. Executing this task in CPUs requires the computing power of 2500 state-of-the-art CPUs and makes it therefore awkward. We describe here a distributed architecture of 120 computing nodes, each consisting of a commodity computer with a PCI FPGA co-processor board inserted, capable to perform the whole track reconstruction, thus achieving a speed-up of 20. Each node processes a full event, making use of the appropriate hardware device (FPGA/CPU) for the particular tasks. Since a full track reconstruction algorithm needs inherently parallel algorithm steps, sequential steps and floating-point arithmetic, a hybrid CPU/FPGA hardware architecture might fit the problem best.