High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques

Field Programmable Gate Arrays (FPGAs) offer very efficient fault-tolerance strategies based on partial reconfiguration. These strategies use dedicated spare resources at different levels to replace faulty elements. A method to determine if the targeted level of reliability can be obtained is then required. In this paper, we generalize the reliability estimation formulas for the state-of-the-art fault tolerance techniques based on partial reconfiguration. We use those formulas to estimate the bounds of the different techniques in terms of reliability level and bitstream overhead. This work makes possible to evaluate early in the design-flow the achievable mission time for a given number of faults per time unit. Thanks to its generality, our approach can be derived for future new partial reconfiguration approaches.