User-Transparent Translation of Machine Instructions to Programmable Hardware

We describe the design and evaluation of a JIT compiler for user-transparent acceleration of loops on FPGAs. We alleviate the need for FGPA CAD tools through an overlay designed for the pipelined execution of dataflow graphs (DFGs). We target systems that tightly integrate processors and FPGAs to share system memory, exemplified by the Intel QuickAssist platform. Our JIT compiler extracts the DFGs of innermost parallel loops in code and configures the overlay to execute the iterations of the loop in a pipelined fashion, improving throughput. Our preliminary evaluation of a functioning prototype of the compiler uses a simulator of the pipelined execution of DFGs on the overlay. It shows that over 72% of the loops in the 30 PolyBench benchmarks can be accelerated. In benchmarks where all loops are accelerated, an average speedup of 2.23X over CPU execution is achieved. The average speedup across all the 30 benchmarks is 1.62X with only three experiencing a slowdown. These results encourage us to continue our work on this approach.