Algorithm and Architecture Design of a Hardware-Efficient Image Dehazing Engine

The function of an image dehazing algorithm restores a hazy image back to a clear one. This technique can be equipped in Advanced Driver Assistance Systems (ADAS) to further improve driving safety. Advanced display resolutions and high frame rates are critical to improve the reliability of ADAS. However, they cause a serious limitation on the hardware realization of an image dehazing algorithm. In this paper, an algorithm and architecture design of a hardware-efficient image dehazing engine are proposed. This dehazing algorithm comprises two core techniques: a low-complexity airlight estimation (LAE) and an independent transmission rate estimation (ITRE). LAE can efficiently predict the airlight without massive sorting processes and a computationally intensive filtering. Moreover, in its hardware architecture, a preluded airlight estimation is proposed to yield an efficient data scheduling. Being independent of the airlight, ITRE is able to solely predict transmission rates. This enables LAE and ITRE to be concurrently processed, improving the throughput of their hardware architectures. Compared with other sophisticated studies, this study demonstrates a competitive performance in peak signal-to-noise ratio, structural similarity, contrast distortion, and computational efficiency. The hardware architecture is realized using Taiwan Semiconductor Manufacturing Company CMOS 0.18-μm technology, and logic gate count is 32.6 K. Its working frequency is 200 MHz with a power consumption of 16.5 mW. The maximum throughput is as high as 600 megapixels/s, which can support 4096×2160 at 60 frames/s. The experimental results indicate that this paper demonstrates superior energy and area efficiencies.