Analysis of Temperature Distribution in Stacked IC with Three Tier Structure

Temperature distribution in three tier stacked IC was analyzed with on chip measurement circuits, which were implemented in a specially designed LSI sandwiched between bottom and top dummy chips. Three kinds of LSI thickness t
_si
= 20, 30 and 50 μ m were fabricated. The temperature distributions were analyzed with on-chip sensor arrays and heater resisters and compared with thermal simulation results. The thinner LSI with the stacked structure showed the higher LSI temperature, and the top dummy chip of the third tier reduced the temperature.