Self-Heating-Effect-Free p/n-Stacked-NW on Bulk-FinFETs and 6T-SRAM Layout

CMOS-device improvements have been recently investigated by changing the geometry of the device from FinFET to nanowire (NW), in which self-heating is serious issue. In this work, we simulate the NW FETs with not only electrical contact but also thermal one from the heat source to wafer. Moreover, we propose the possibility of self-heating-effect-free 6T-SRAM using p/n-stacked-NW on bulk-FinFETs with recessed contact.