Investigation on maximal throughput of a CMOS repeater chain

This paper investigates the performance of a simple repeater chain interconnection for high-speed on-chip data transfer. The data in the repeater chain is distributed over a number of identical inverters, which are optimized with respect to size and position along the chain. It is shown how the distributed interconnection compares, in terms of throughput and power consumption, with a lumped driver consisting of several cascaded inverters with a stage ratio larger than one. The performance of the repeater chain has been demonstrated by design and measurement of a 0.8-/spl mu/m twin-well double-metal single-poly CMOS chip, in which a 4-mm repeater chain had a maximal data rate of 1.7 Gb/s at V/sub dd/=5 V.