A 25-Gb/s 270-mW Time-to-Digital Converter-Based $8{\times}$ Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS

This paper presents a time-to-digital converter-based oversampling input-delayed multi-standard adaptable data-receiver architecture which digitizes transitions/threshold-crossings and inter-transition distances inside a time-varying binary input symbol sequence. The presented circuit works by sampling delayed replicas of a threshold-crossing binary input symbol sequence inside a differential delay-line. The resulting sampled digital word carries information of the threshold-crossings and the distances between them. The proposed 64-tapped adaptable-delay-line-based design is intended as a high-rate oversampling baseband binary quantizer for a high-speed serial link. The data-receiver has been demonstrated to digitize up to 25-Gb/s input binary symbol sequences with an oversampling ratio of eight. Designed in a 45-nm SOI CMOS process, the receiver circuit is fully characterized by applying different symbol sequences at its input while setting its time resolution and dynamic-range/delay to 5 and 320 ps, respectively. Under these conditions, the data-receiver consumes 270 mW of power, and achieves an energy conversion figure of 1.62-4.32 pJ/sampled-digital-bit. The circuit occupies 0.24 mm
²
of active silicon area. The proposed receiver offers one of the highest time-resolution and oversampling factor, and among the best energy conversion figures compared with the oversampling time-mode receiver architectures reported so far.