A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

This work describes the implementation of a discrete cosine transform (DCT) core compression system targetted to low-power video (MPEG2 MP@ML) and still-image (JPEG) applications. It exhibits two innovative techniques for arithmetic operation reduction in the DCT computation context along with standard voltage scaling techniques such as pipelining and parallelism. The first method dynamically minimizes the bitwidth of arithmetic operations in the presence of data spatial correlation. The second method trades off power dissipation and image compression quality (arithmetic precision). The chip dissipates 4.38 mW at 14 MHz and 1.56 V.