An analytical model for breakdown voltage of surface implanted SOI RESURF LDMOS

An analytical model for the breakdown voltage of the surface implanted silicon-on-insulator (SOI) REduced SURface Field (RESURP) LDMOS is presented, which allows useful design curves of breakdown voltage in terms of the device parameters, including the substrate bias voltage. Improvement on both the breakdown voltage and the on-resistance of the device due to the surface implantation is demonstrated. Numerical simulations are shown to support the analytical results.