A Robust and Self-Adaptive Clocking Technique for SFQ Circuits

Living on the verge of the IoT era, the entire world is excited about the potential of mining the monumental amounts of data that would become available in the near future. However, this increasing abundance of data requires supercomputers faster and more powerful than were ever built without the need to build a nuclear plant next to each one! Single flux quantum (SFQ) technology has the potential to meet those booming demands for lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Nevertheless, the promised benefits of three orders of magnitude lower power at an order of magnitude higher performance have yet to be attained. In particular, variability and scalability have been long-term obstacles for the technology to advance, compete, and replace the well-founded Silicon CMOS. Notwithstanding that SFQ fabrication has quite improved over the past two decades, its level of variability has to be taken into design consideration. Moreover, the absence of an established tools flow hinders the scalability and the automatibility, which are among the trumps of CMOS technology in digital VLSI. Specifically, as a consequence, ultra-high-speed clocking of large-scale SFQ circuits in the presence of large levels of variability represents a tough obstacle for the technology to advance. In this paper, we propose an innovative self-adaptive clocking technique, which is designed to be resilient in such uncertain environments. Whereas the traditional balanced tree zero-skew clocking is not reliable for large-scale SFQ designs, our proposed hierarchical chains of homogeneous clover-leaves clocking inherits its robustness from spatially correlated cell delays and from the timing robustness of the SFQ traditional counter-flow clocking. Our simulations on ISCAS'85 benchmark circuits show that our robust clocking costs can be on average within 34% as fast as ideal zero-skew jitter-free clock trees with an average area overhead of 58%. Moreover, lower area overhead is also possible at the cost of performance, demonstrating the possible trade-off between performance and area. We assert that these overheads are acceptable given the benefits of more reliable functionality, as quantified by yield, as well as improved scalability. In particular, previous efforts reported that a similar, but more limited, clocking structure leads to up to 93% higher yield than zero-skew clock trees.