A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals

A 9.1ENOB 200 MS/s asynchronous SAR analog-to-digital converter (ADC) dealing with image sensing signals is presented in this paper. The proposed ADC, designed in 55-nm CMOS process technology, can work in both single-ended and differential modes. To guarantee the ADC linearity, a symmetrical switching method is adopted. To ensure the reference accuracy when the ADC is in operation, a 1.2-V on-chip quick-response LDO, which works under a 2.5-V supply, is also integrated. To overcome the need for a clock-generation circuit and avoid a high-speed interface circuit design, asynchronous clock logic is chosen. In addition, the comparison cycle is adjusted dynamically to guarantee the DAC settling and improve the ADC throughput. In the differential operation mode, the proposed SAR ADC exhibits a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB and a peak spurious-free-dynamic-range (SFDR) of 68 dB with the Nyquist input, at a 200-MS/s output rate. The ADC consumes 2.74 mW, resulting in a figure-of-merit (FOM) of 25-fJ/conversion-step. Meanwhile, in the single-ended mode, the SNDR and SFDR of the ADC are 53and 64 dB, respectively. And the power consumption is 2.25 mW, resulting in an FOM of 31-fJ/conversion-step. The area of the proposed ADC is 280 × 380 μm
₂
and the ADC core occupies an active area of only 140 × 250 μm
²
.