Heap Queue: A Novel Efficient Hardware Architecture of MIN/MAX Queues for Real-Time Systems

This paper presents an efficient hardware architecture of min/max queue, which is suitable for real-time systems due to the constant response time of the queue. This architecture, called Heap Queue, can sort items according to their sorting values and can remove the first item from the queue. The instructions of the Heap Queue architecture have throughput of one instruction per two clock cycles regardless of the actual number of items in the system and regardless of the queue capacity. The developed queue was implemented in FPGA. Achieved synthesis results are presented and compared to the synthesis results of the Rocket Queue architecture. Advantages and disadvantages of the proposed Heap Queue architecture in comparison to the Rocket Queue architecture are discussed.