Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this paper. Emphasis is placed on the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. The electroless Cu is used to make the seed layer, the laser direct imaging is used for opening the photoresist, and the printed circuit board Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the drop test and thermal cycling test are also performed.