Implementing on the field programmable gate array of combined finite state machine with counter

A method for heterogeneous implementing the circuit of combined finite state machine on the field programmable gate array is proposed and oriented especially to the high-reliable ProASICs. The method is based on constructing the set of linear chains of states and replacement of the state register by counter. Encoding of classes of pseudoequivalent states is used for diminishing the number of memory excitation function arguments. An example of combined finite state machine synthesis using the initial graph-scheme of algorithm is considered.