Single clock square root algorithm based on binomial series and its FPGA implementation

Signal processing is frequently discussed topic nowadays. Digital Signal Processors (DSP) or Field Programmable Gate Array (FPGA) can process data at high rates. Arithmetic operations such as addition, subtraction, multiplication, division or square root are often used in DSP and FPGA. Several algorithms for square root computation on FPGA were designed in past years. This paper describes a proposal of single clock square root algorithm applicable on FPGA. The algorithm is formulated generally for any number of bits. Simulations and experiments for 16-bits binary numbers have confirmed that obtained results are equal to square root values rounded to nearest integer.