Design of WOLA FFT based channelizer

The channelizer techniques that are common in use are examined in this thesis and weight overlap and add(WOLA) channelizer technique is designed in the MAT LAB Simulink platform and its advantages and disadvantages are examined in details. In the design phase, channelizer makes compatible for use with Xilinx FPGA family. VHSIC hardware identification language (VHDL) code of the channelizer that was designed on MATLAB Simulink is developed and synthesized on the Xilinx ISE platform. So, the resource utilization of the channelizer that was designed in the FPGA can be calculated.