Efficient Low-Latency Implementation of CORDIC-Based Sorted QR Decomposition for Multi-Gbps MIMO Systems

This brief presents the efficient VLSI implementation of coordinate rotation digital computer (CORDIC)-based sorted QR decomposition (SQRD) for multiple-input and multiple-output (MIMO) systems. SQRD is widely adopted in MIMO signal processing to mitigate error propagation. However, its iterative sorting process after every column annihilation requires a large hardware overhead and suffers from a latency issue. The proposed CORDIC-based SQRD modifies a real-value decomposition matrix to utilize symmetry and jointly performs sorting processes and CORDIC rotations with adjacent symmetric columns to reduce the required number of CORDIC rotations and CORDIC stages. Furthermore, the VLSI design of the proposed SQRD has been synthesized and implemented with a Virtex-6 FPGA and a 65-nm CMOS technology, respectively. The 65-nm implementation results show an overall processing latency of 266.5 ns, a throughput of 48.8 MSQRD per second, and can support a 4.7-Gbps MIMO system throughput.