A 0.6-V, 74.2-dB DR Continuous-Time Sigma–Delta Modulator With Inverter-Based Amplifiers

This brief presents a 0.6 V third-order continuous-time sigma-delta modulator (CT-SDM) based on single-stage inverter-based amplifiers. The designed amplifier uses an onchip bulk-bias technique to control the common mode output voltage and to mitigate process, voltage and temperature variations. Also, a negative resistance is used at the output of the amplifier to enhance dc gain. To increase power efficiency, a single-amplifier resonator is used in the loop filter. To enable this implementation a compensation technique to mitigate the effects of amplifier's finite dc gain in the resonator transfer function is presented. The proposed CT-SDM was fabricated in a 130-nm CMOS process with an active area of 0.232 mm
²
. The modulator achieves a 74.2 dB DR and peak SNDR/SNR of 59.43/69.04 dB for a 100 kHz signal bandwidth while consuming 89.50 μW from a 0.6-V power supply.