Derating of Parallel SiC MOSFETs Considering Switching Imbalances

This paper presents a numerical method used to analyse the parallel connection of several SiC MOSFET dies. Parallel connection is necessary to achieve the desired current carrying capability of main inverters for xEV-drives. With this method the effect of asymmetries within the chips' parameters, especially the threshold voltage, are investigated. The investigation results quantify to what extent the PTC behaviour of the on-state resistance can mitigate the overheating of one chip caused by switching loss imbalance. The results are used to define the necessary derating of the inverter output power, so that no single chip is thermally overstressed.