Power Bounds and Energy Efficiency in Incremental $\Delta\Sigma$ Analog-to-Digital Converters

Incremental analog-to-digital-converters (IADCs) are variants of ΔΣ ADCs, which have been increasingly used for low-power sensory applications in recent years. Most IADC applications require high resolution and high energy efficiency. In this paper, we present a systematic analysis of IADCs. We derive analytical design equations for practical IADC designs. Process limitations are included in the model as well. The equations are verified with a 14-bit second-order IADC design in a 0.18-μm process. With the design equations, the theoretical energy efficiency bound is derived for IADCs. The efficiency bound is compared with previously reported IADC designs. It is found that the derived bound matches existing designs well.