Analysis and Design of a 200-GHz SiGe-BiCMOS Loss-Compensated Distributed Power Divider

This paper presents the first demonstration of an active power divider operating from 100 MHz to 200 GHz. The circuit is based on a distributed architecture, where two output lines are fed replicas of the signals traveling in the shared input line. The gain element employed in the distributed divider consists of a triple-stacked cascode that exploits internal feedback to increase its equivalent transconductance. The higher transconductance toward frequency compensates the synthetic-line losses, which are the main limiting factor for applications at high frequencies of this class of circuits. A tapering of the synthetic-line impedance has also been adopted to further minimize the synthetic losses. Implemented in a high-performance 130-nm SiGe-BiCMOS technology, the system requires 300 mW of dc power consumption to provide 10 dB of gain over the 3-dB bandwidth 1-180 GHz. At 100 MHz and 200 GHz, the gain decreases to 0 dB. The presented circuit improves the state of the art for distributed power dividers implemented in any integrated circuit technology by a factor 5 for both maximum frequency of operation and bandwidth. Thanks to the triple-stacked gain cell in combination with the tapered synthetic line, the circuit reaches 10 dBm of output power at 1-dB gain compression, which is the highest reported for distributed power dividers.