Evaluation and comparison of mounted inductance for decoupling capacitor

In this article, different patterns for decoupling capacitor routed on a dedicated test vehicle are compared. The aim of this study is, on one hand to confirm design rules for enhanced decoupling on printed circuit board and on the other hand, to estimate the value of the mounted inductance introduced by each pattern. Each mounting pattern and the particular parameter which is studied for each case will be described and measurement methodology as mounted inductance calculation will be presented. Then, mounted inductance calculated from measurement and results given by simulation are compared in order to see the precision reached by recent hybrid EM solver dedicated to Printed Circuit Board for parasitic elements calculation. Finally design rules and trade off for better decoupling are given as a conclusion.