Simulation study on the high-k SJ-VDMOS with gradient side-wall

The influences of gradient side-walls in a High-k Super Junction Vertical Double-Diffused Metal-Oxide-Semiconductor (High-k SJ-VDMOS) and in an ordinary Super Junction VDMOS (SJ-VDMOS) are studied and compared according to the analysis and simulations. The two devices show the same steady on-state current density for different side-wall gradient, but their breakdown voltages (V
_b
) acutely vary and, therefore, their FOM (Figure of Merit, which is equal to the square of V
_b
divided by the specific on-resistance) are varied. The study indicates that, the V
_b
of the device with more lightly doped pillars will be less impacted by the side-wall gradient, and the one having the pillars with unequal areas will be more impacted. Moreover, it is also demonstrated that, an appropriate positive side-wall gradient (namely, the Hk-pillar is wider at the top than at the bottom) would significantly benefit the V
_b
and FOM. The comparisons between the High-k SJ-VDMOS and the ordinary SJ-VDMOS prove the former is more resistive to the side wall gradient deviation. Meanwhile, these study results are believed to be a useful and helpful reference to improve the High-k SJ-VDMOS.