Sense amplifier offset cancellation and replica timing calibration for high-speed SRAMs

A CMOS SRAM design in 130 nm BiCMOS SiGe technology is presented. A 10 Kb array was designed to operate at a 500 MHz clock and a 1.5 V supply. The SRAM array is implemented in four 2.5 Kb quadrants with shared column and row addresses and local quadrant decoding. A calibrated and tunable replica timing structure technique is used to generate optimal sense amplifier (SA) enable timing by replicating both column and row delay of the memory simultaneously using replica bitline and replica wordline structures. A new capacitive offset cancellation technique for current-mode SA is proposed. Using replica timing and capacitive offset cancellation techniques optimizes operation speed for the most process-invariant timing and smallest SA area. Monte Carlo simulations were performed on both the current mode sense amplifier with capacitive offset cancellation (CSA
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), and a conventional latch type CSA without offset cancellation for 200 runs of process and mismatch. The CSA
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performed without read failures across the design space at ~100 ps faster read access time with 50% less SA area.