Educational design kit for synopsys tools with a set of characterized standard cell library

ON Semiconductor 500 nm process (ONC5) is a well establish technology for educational IC development. However a full design flow in native rules is not offered for Synopsys tools. This paper describes the construction of an Educational Process Design Kit (PDK) with full digital and analog flow, Standard cell library and Special Cells. The PDK includes a library of 100 characterized standard cells, which supports clock gating and design for testability techniques that allow fast digital IC development. It also has a set of Parametric Python Cells for analog development. These components of the PDK improve any type of mixed-signal design for educational and research purposes.