Evaluation of compensation techniques for CMOS operational amplifier design

This paper presents and compares two CMOS (complementary metal oxide semiconductor) operational amplifier (op-amp) designs. Each op-amp is based on a two-stage rail-to-rail output where the first stage is a differential input with folded cascode and the second stage forms a class-AB amplifier. Each opamp design incorporates different compensation techniques. The first op-amp uses negative Miller compensation around the first stage and conventional Miller compensation is used around the second stage. The second op-amp also utilizes negative Miller around the first stage, but with indirect Miller between the output node of the second stage and cascode node of the first stage. The purpose of this work was to evaluate the DC gain, unity gain frequency (UGF) and phase margin (PM) achieved using the different compensation techniques in simulation and test results from physical prototype devices using a 0.35 μm CMOS technology when operating on a single rail +2.5V and +1.8 V power supply.