Adiabatic approach for charge restoration in low power digital circuits

The main idea dominating the current trends in VLSI circuits is to offer large scale integration coupled with extensive power reduction solutions, even with newer devices and topologies[1]-[2]. However the significant increase in the gate switching energy results in higher power dissipation and costly heat sinks. At that point, to constrain the dissipation of power, elective arrangements at various level of deliberation are suggested. The power dissipation is significantly reduced by the adiabatic logic structure at the expense of circuit complexity to accomplish low power dissipation, switching procedures are used. Adiabatic logic discussed here provides an approach to use the energy repeatedly that is put away in the load capacitors. This paper briefs some of the adiabatic logic families such as PFAL and SAL. It aims at comparing the effectiveness of adiabatic logic with respect to power dissipation and delay. The implementation of the 4 bit CLA validates the credibility of the logic. A graph has been plotted to show the effect of temperature on sub threshold adiabatic logic based 4 bit CLA. The simulation results obtained from the vituoso environment of cadence tool suggests three folds power reduction in the ECRL topology as compared to the other existing topology.