FPGA implementation of Parity Check Matrix based Low Density Parity Check Decoder

Low Density Parity Check (LDPC) error correction decoders have become popular in diverse communication systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. Low Density Parity Check Decoder is a class of Forward Error Correction Codes. The parameterization of a particular LDPC code is defined by its Parity Check Matrix. Parity Check matrix which describes the specific logical combination of the transmitted message bits into parity checks. PCMs are sparse matrices having far more zero entries than nonzero. It allows LDPC codes to be iteratively decoded using a low complexity message passing algorithm. Thus the objective of this project is to implement a PCM based LDPC decoder architecture on FPGA. Initially the components of LDPC decoder are identified then Verilog HDL coding for these components have been written, simulated using Altera Quartus II software. The implementation of these components are done on Altera Cyclone II FPGA kit to improve the error correction performance of communication system.