Impact of radices for the design of efficient FFT processor

Fast Fourier transform (FFT) is always an accepted topic for research from past many years for different applications in digital system. Implementation of FFT processor is an active growing field with possible advances. This work focuses on datapath unit of a FFT processor and presents low complexity and less area consuming datapath unit of FFT by combining algorithms, arithmetic and architecture. Implementation of radix-2, radix-4 and radix-2∧2 FFT algorithm will be done using different types of multipliers such as Array multiplier, Vedic multiplier and different type of adders like Ripple carry adder and Carry save adder which are represented in fixed point (Q-format) for N=8, 16 points. Synthesize is done to know the performance of LUTs, delay (ns) and Frequency (MHZ) of different radices. Simulation is performed using Verilog code on Spartan6 family. Xilinx ISE 14.7.