A Discrete-Time RF Signal-Processing Technique for Blocker-Tolerant Receivers With Wide Instantaneous Bandwidth

A new signal-processing approach aimed at improving the intermodulation performance of wideband receivers implemented in CMOS technologies is described. The receiver operates by downconverting an input signal to N decimated baseband signals. The local oscillator signals used in this process are each a different phase of a pseudo-random bit sequence of length N. The baseband signals are amplified and digitized before the original RF signal is reconstructed in the digital domain. The operating principles of the system are described and the performance specifications of this system are studied using a combination of analytical and numerical techniques. A prototype integrated circuit has been designed and fabricated using a 130-nm CMOS process. Detailed measurements demonstrating the narrowband and wideband operation of the system are presented and compared to theory. The measured in-band I I P3 has been found to be greater than 5.7 dBm from 40 to 300 MHz. The blocker tolerance of the circuit has also been characterized and it was found that a 10-MS/s -50-dBm 16-QAM signal could be received with nearly constant error-vector magnitude as the power of an in-band blocker signal was swept from -20 to -7 dBm.