1 GHz fully pipelined 3.7 ns address access time 8 k/spl times/1024 embedded DRAM macro

This macro is designed as a DRAM cache for a future gigahertz microprocessor system based on a logic-based DRAM technology. The most notable feature of this macro is its ability to run synchronously with a gigahertz CPU clock in a fully-pipelined fashion. It operates with a 1 GHz clock signal at 85/spl deg/C, nominal process parameters, and a 10% degraded V/sub DD/. The design is fully pipelined and synchronous with 16 independent subarrays. The address access time is 3.7 ns, four cycles with a 1 GHz clock. The subarray cycle time is 12 ns.