A 1 GHz portable digital delay-locked loop with infinite phase capture ranges

Delay-locked loops (DLLs) are widely used to align signal phases in many high-speed microprocessors and memories. Phase-locked loops (PLLs) are also used but their jitter is larger than that of DLLs, because DLLs have no jitter accumulation. However, conventional DLLs have design problems. One is that their phase capture ranges are limited, and another is that a special reset sequence is required. Dual DLL architectures are developed to overcome these problems. In these architectures, the latency from the input to the output, however, is lengthened to attain high resolution, because these architectures require a number of multiplexers between the DLL input and output ports. As a result, supply-noise induced jitter increases. To reduce the jitter, a portable digital DLL uses the following techniques: (1) a master-slave architecture, which achieves infinite phase capture ranges and eliminates the special reset requirement, (2) a wave synchronous latch circuit, which maintains high resolution, and (3) a dynamic phase detector, which improves phase comparison sensitivity.