An embeddable low power SIMD processor bank

Existing digital imaging systems have high computational requirements for real-time image processing and/or real-time video compression. A parallel SIMD processor architecture is capable of performing several types of image processing tasks such as image filtering, image correlation and a modified vector quantization (VQ) image processing algorithm. The SIMD processor is suited for embedding with a digital CMOS imager by pitch matching 16 CMOS pixel columns to a multiplexed 128/spl times/8b streaming data buffer (SDB) and processing element (PE) with 13b data path. A prototype SIMD processor with 8 PEs in 0.6 /spl mu/m CMOS technology demonstrates performance for real-time video compression of raw 640/spl times/480 color images at 30 fps to <1 b/pixel while consuming <40 mW at 10 MHz and 2.5 V. A full-scale embedded SIMD processor requires /spl sim/50% additional area compared to 640/spl times/480 for digital CMOS imager alone.