A 600 MHz 64 b PA-RISC microprocessor

This 64 b processor is a leveraged design based on the previous generation with the goal of a 1.2X performance increase on a short schedule in the same 5 metal layer, 0.25 /spl mu/m CMOS process. Speed path and clock tuning techniques increase the operating frequency. To reduce the cache miss rate, a quasi-least recently used (LRU) replacement algorithm is implemented using a LRU cache. The data cache on the quad issue processor is a 1 MB, dual ported, four way set associative design implemented on the die using 64 B per cache line.