A 0.6 W 10 Gb/s SONET/SDH bit-error-monitoring LSI

A low-power 10 Gb/s SONET/SDH monitoring LSI uses Si bipolar process. This is the first monitoring LSI operating at 10 Gb/s. The LSI monitors the bit errors in 10 Gb/s SONET/SDH frames using a parity byte B1. The LSI architecture is optimized for monitoring. The descrambler, which restores the incoming scrambled signal, is omitted to reduce power dissipation. The LSI can cope with 10 Gb/s and 2.5 Gb/s frame formats by using a multi-frame-format counter/decoder. The framer/demultiplexer is composed of a byte-aligning demultiplexer and a frame detector.