Cache fault injection with DrSEUs

Operating processor devices in space environments is challenging due to radiation strikes, which can cause a device to fail or fault. Caches are of particular interest in radiation effects research because they occupy a large portion of a device's area, and therefore account for a significant proportion of Single-Event Upsets (SEUs) within a device. Unfortunately, caches are difficult to access directly and impossible on most hardware testbeds. This paper presents the methodology for injecting faults into processor caches using our Dynamic Robust Single-Event Upset Simulator, DrSEUs. DrSEUs leverages the Simics full-system simulator to provide simulation-based, fault-injection capabilities. Simics provides tools to build cache models for simulated devices (but not included by default). However, these models are intended for collecting timing information and do not contain cache contents. In order to support fault injections, we have modified the g-cache Simics extension to include cache contents and added support to DrSEUs for targeting the simulated cache objects. We demonstrate and evaluate the injection capabilities and analysis features of DrSEUs by presenting cache fault-injection results for an image-processing application.