Performance modeling, design and FPGA-based validation of digital transparent satellite processors

In satellites communication systems digital semi-transparent payloads have been recently devised and investigated to obtain architectures with potentials i) to operate with enhanced frequency planning flexibility and physical layer specifications of evolving communications standards, and ii) to support dynamic reconfiguration of connectivity plans. The related architectures consist of a) a main digital transparent section devoted to the routing of the bulk of traffic data and denoted as Digital Transparent Processor (DTP), and b) a companion digital regenerative block that handles the much smaller amount of control data related to media access control. In our recent works a quantitative framework for performance analysis of a DTP, based on an extended notion of noise figure, and an explicit computation of implementation complexity have been provided to achieve feasible trade-offs between hardware efficiency and overall link-budget performance. The present paper addresses the DTP section and is concerned with application of the above developed framework to an extended set of system scenarios suggested by various use cases. Specifically, the impact of the overall processed bandwidth and routing flexibility requirements is investigated. Furthermore, a significant novel contribution comes from validation of the design choices in the DTP chain that are obtained through an FPGA-based prototype benchmark that has been specifically developed in our lab.