A segmented resistor-string DAC based stimulus generator for ADC linearity testing

This paper presents a segmented resistor-string digital-to-analog converter (DAC) based stimulus generator for analog-to-digital converter (ADC) linearity testing. By using the folded main resistor string, the capacitive loading is reduced to enhance the operating speed of the DAC. The complexity, the number of unit resistors, and the area cost of the DAC are reduced by using the parallel-connected sub-resistor strings. The theoretical analyses of the area cost, settling behavior, and the integral/differential non-linearities (INL/DNL) are presented to evaluate the trade-offs among the performance of the proposed DAC, the design parameter, and the mismatch of the resistor. Due to the features of simple structure and low capacitance loading, the proposed DAC is combined with a field-programmable gate array (FPGA) device and other circuitry to practically generate a ramp stimulus for ADC linearity testing. The testing result by using the proposed segmented DAC based stimulus generator shows a certain agreement to that by using the expensive instrument.