2×VDD-tolerant ESD detection circuit in a 90-nm low-voltage CMOS process

A new 2×VDD-tolerant electrostatic discharge (ESD) detection circuit using only low-voltage device is proposed in a 90-nm 1-V CMOS process. Unlike the RC based detection circuit, the proposed circuit is a voltage triggered detection circuit, so the clamp device cannot be triggered even under very fast power up events. Also, without RC network the detection circuit generates a very small leakage current. The proposed circuit can generate 50.1 mA current to turn on the substrate triggered silicon-controlled rectifier (STSCR) under the ESD stress. Under normal operating conditions, all the devices are free from over-stress voltage threat, the leakage current is only 50 nA. The simulation result shows the circuit can be used for 2×VDD-tolerant application.