A loop transformation technique for timing speculative architecture

Traditional processor design incorporates voltage and frequency guardbands to ensure correct execution of operations under worst-case conditions. As transistor density increases and manufacturing processes improve, increasingly costly guardbands are required to deal with the impacts of environmental variability. The use of timing speculation can relax the tight constraint for worst-case design by allowing occasional errors, which are detected and corrected later by an error resilience mechanism. However, a program's performance may suffer owing to timing errors. This paper analyzes program behaviors and proposes a loop transformation technique for timing speculative architectures. We observe relationships between program behaviors and timing errors through a simulator. From the analytical results, a loop transformation technique is developed to reduce timing errors. It is implemented and evaluated using LLVM compiler infrastructure. For the tested benchmark programs, the proposed loop transformation can reduce timing error counts by up to 37%.