Investigation on degradation mechanism and optimization for SiC power MOSFETs under long-term short-circuit stress

In this paper, the degradation mechanism of silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under long-term short-circuit (SC) stress is investigated. With the help of Silvaco TCAD simulations and measurements on degraded parameters, the injection of electrons into gate oxide above channel region of the device is demonstrated to be the dominant degradation mechanism. It results in the positive shift of threshold voltage (V
_th
) and the increase of on-state resistance (R
_dson
) under low gate voltage bias condition. Simulated electrical properties of the device with electrons trapped into gate oxide above channel region share similar degradation trend with measured ones, proving the correctness of our analysis. Furthermore, an improved device structure with an additional shallow inverted-doping p-well, which can effectively lower the impact ionization rate (I.I.) along the SiC/SiO
₂
interface above channel region during SC process, is proposed to restrict the degradations under long-term SC stress.