Novel approach for NLDMOS performance enhancement by critical electric field engineering

Novel design approach for LDMOS device operating at voltages exceeding 100V is demonstrated and architecture to address all aspects of critical electric field is described. As a bonus, no changes in doping conditions required to achieve the device targets. This paper presents a design study for a resurf layer to engineer the critical electric field in LDMOS device. Results provide guidance on how to push high electric field lines away from the surface and how to successfully align them in the direction of the current. The new architecture is intended for small devices where area saving due to smaller isolation brings another benefit. This approach is compared with conventional single resurf design that normally unable to meet these conditions. LDMOS device breakdown is designed to predominantly occur underneath the drain of the device to avoid interaction with the gate oxide. Finally, results in this publication show how reversing source and drain can improve ESD ruggedness.