An evaluation power model for TriBA based application mapping and memory-on-chip

An application mapping algorithm is proposed for using the multicore architecture TriBA. Meanwhile a power consumption evaluating model based topology of on-chip memory network design is presented after application mapping strategy onto various multicore architecture topologies. This paper focuses on evaluating power of on-chip memory and communication network based the approaches of Kernighan-Lin tri-partitioning algorithm strategy. Utilizing the average hops of links between the components in System-on-Chip, this method computes the average hops which instructions access memory network and communication network on chip. Experimentations with the average hops and established benchmark VOPD show that the proposed method not only can quickly and effectively estimates power consumption but also direct the improvement of Network-on-Chip architecture by using the same application mapping strategy based on topology of multicore architectures.