Design and simulation of FPGA based all digital phase locked loop (ADPLL)

Phase locked loops are most widely used in communication systems. Most of the PLL's that are used currently are hybrid type PLL's, where only the phase detectors are digital where as voltage controlled oscillators and loop filters are analog. This article presents an all digital approach for the design, simulation, Synthesis, and implementation of FPGA based ADPLL centred at 196 KHz with a lock range of 10% using VHDL codes. Xilinx ISE Design Suit 14.5 tools is used for simulating VHDL Codes and Xilinx Spartan 6 LX45 FPGA board for implementation. The FPGA results are verified using chipscope pro analysis tool. FPGA implementation results showed conformance with regard to the simulation results. The proposed design methodology resulted reduction of resources by 42% and low process time of 8.11ns as against 12.99ns achieved by other design methodologies.