Study of Counter-Pulse (CP) Programming Method to Improve the Vt Distribution for 3D Charge-Trapping NAND Flash Devices

The charge-trapping devices used in 3D NAND Flash often possess certain fast initial charge loss behaviors, leading to degraded programming distributions. A possible design method to improve the programming distribution is to insert an additional programming phase named as "counter-pulse" (CP), which is applied immediately after +FN programming but just before the program verify (PV). Such CP programming method is verified to be very useful to tighten the PV distribution for better memory window. In this work, CP programming method is studied extensively in order to optimize the memory window and programming performance for a SGVC 3D NAND Flash product chip.