Analysis of network topology processor algorithms in substation level networks

The network topology processor presented takes the bus-section/switching device model of the power system network and uses the data on the status of all the circuit breakers and switches in the power system network to build the bus/branch model for the given power system network. Different substation processing levels were developed for updating the data table and the network configuration table. Two network topology processing algorithms were developed in terms of three modular sections are described. The output of the network topology processor is used for analysis of the power system network. The works aims at building and analyzing different levels of the network topology program which is implemented in matlab, Several test case scenarios were considered for a seven substation model using this network topology processor program.